Throughout the 1970s and 1980s semiconductor packaging was relatively stable, with changes occurring gradually over periods of five to ten years. The U.S. military was the major technology driver--controlling standards, testing and managing change. During the 1970s, one major focus in packaging was in cost reduction--producing a semiconductor package at lower cost. From 1984 to through 1994, change was gradual, the largest change being a gradual transition to surface mount technology (SMT). Over that ten year period, approximately 50% of the industry converted to SMT, which illustrated how slowly new technologies may be introduced into electronics packaging.
However, with the growth of the consumer and industrial electronics industry and the simultaneous decline of the military market, rapid changes have occurred in the electronics industry. As a result, the U.S. electronics market may be starting to operate much like the Japanese consumer electronics market--with higher pressures to reduce costs and shrink packaging size.
To meet such demands, integrated circuit (IC) manufacturers have begun integrating more circuit functions, shrinking device features, and increasing speeds. From a packaging perspective, smaller form factors, requirements for more input/output signals and power management all became major technology drivers. System level needs included the transition to SMT and use of finer featured packages. Sophisticated new products of all types began developing, and soon barriers were reached with conventional packages and processes.
Conventional package leads may be deemed too fine and fragile, and surface mounting processes have not proved to be robust enough to provide acceptable yields. The 208-lead Plastic Quad Flat Package (QFP), illustrated in FIG. 8, became the appropriate practical limit for peripheral leaded packages--and the transition to grid array packages began.
To further enable compatibility with surface mount technology (SMT) process, solder balls were attached at the bottom of land grid array packages, forming the Ball Grid Array (BGA), illustrated in FIG. 9. The BGA package allows for much greater I/O counts while eliminating the fragile and difficult aspects of the conventional QFP.
A number of derivatives of the BGA (e.g., FPGA, .mu.BGA, or he like) are in existence today. The BGA package comprises a ceramic substrate with a multi-layer interconnect. On the top of the package, a single die or multiple dice may be attached by wire bond or flip-chip to the substrate. The bottom of the package comprises of an array of solder balls with diameters ranging from 0.4 mm and higher.
For improved reliability, an under-fill maybe used to fill the space between the solder balls following solder attach of the BGA package. A number of variants of the BGA structure may be based on the use of different substrate material including ceramic in CBGA, plastic encapsulated FR-4 in PBGA and flexible circuits in FBGA.
BGA packages were first designed by Motorola to solve space constraint problems in portable communications products. Motorola initially used a 2 layer PCB as a package substrate and in manufacturing, used conventional die attach, bonding, molding and solderball attach. Such a design provided a robust yet small footprint package, used to package lower I/O communications chips.
Soon others manufacturers tested packages in higher pin count applications. It quickly became apparent that BGAs could enable cost effective high I/O packages without causing major manufacturing changes for users. In fact, the BGAs were so robust most users report a 10.times. or greater reduction in solder defects. BGAs enabled great improvements in users manufacturing efficiencies and corresponding cost reductions. BGAs also provided superior electrical performance, as electrical paths were shorter and power/ground planes could be added to the package.
Although BGA structures have inherent high yield assembly, the long term reliability of the interconnect may be compromised without the use of under-fill. Also, these packages are associated with perimeter array contacts which have potentially greater parasitics which may degrade the electrical performance of high clock rate applications.
For package de-mountability, a number of area array interposers/electronic connectors have been developed, and are described below. Each of the approaches uses an area array configuration to form an electrical connection between two parallel substrates which may be clamped or secured together. This connector type can be traced back to July of 1970, with U.S. Pat. No. 3,638,163. Subsequent developments used metallized and metal filled elastomeric cylinders within an array as described in U.S. Pat. No. 3,985,413.
AMP has developed the Micro Interposer.TM. that is based upon an area array separable socket-connector constructed with the aid of a miniature structure which resembles the shape of an omega. The Micro Interposer.TM. uses a retaining housing and when compressed into its contacting position, provides low resistance contacts. The Micro Interposer.TM. is formed by inserting the contacts into cavities formed in photo-defined laminates. Further details of the Micro Interposer.TM. are disclosed in AMP Journal of Technology, Vol. November 1, 1991 (D. G. Grabbe and H. Merkelo), incorporated herein by references.
Another concept developed by AMP uses canted coiled spring contacts positioned in openings within the connector to provide electrical contact between the two intended substrates. In U.S. Pat. Nos. 5,007,842 and 5,030,109 both of which are incorporated herein by reference, the above approach describes the coiled spring contact. This coiled spring contact approach is also disclosed in an earlier U.S. Pat. No. 4,655,462, incorporated herein by reference, which also used canted springs between parallel substrates.
Another concept developed by AMP uses a conductive gel inserted into cavities within an elastomeric body again to form interconnections between two parallel substrates. The structure, described in U.S. Pat. No. 5,123,849 incorporated herein by reference, illustrates how this area array connector could be used to interface an active component to an interconnect substrate.
Through use of miniature springs, E-tec Interconnect has developed an interposer/socket technology for area array devices. The springs may be compressed between two mating members within a fiberglass laminate structure with drilled holes for the vertical interconnect assembly. The solder-less version of their product line has many characteristics of an interposer.
The minimum possible pitch on the E-tec interconnect devices approaches 1 mm with an insertion force of approximately 35 grams per contact. This technology has been used as an area array socket due to its overall size and thickness. In addition, the high cost and no viable path to high volume manufacturing has limited to impact of the technology.
The semiconductor industry, in conjunction with several technical committees and associations have developed road maps for development of next generation products and associated technologies. Industries such as computing, communications and portable electronics have been driving these requirements and the associated road maps.
As an extension of the semiconductor industry, the electronics packaging industry has also witnessed similar technological and market dynamics. Packaging and materials engineering and development are at the very core of these next generation electronics insertion strategies outlined in these road maps. Future electronic systems may be more intelligent, have higher density, use less power, operate at higher speed, and may include mixed technology devices and assembly structures at lower cost than today.
The rapidly growing portable electronics market, e.g. cellular phones, laptop computers, and PDAs, are an integral facet of modern life. The multitude of portable devices represents one of the largest potential market opportunities for next generation packaging. These devices have unique attributes which have significant impacts on manufacturing integration, in that they must be generally small, light weight, and rich in functionality and they must be produced in high volumes at relatively low cost.
Current packaging suppliers are struggling to accommodate the high speed computer devices which are projected to exceed one GigaHertz (GHz) in the near future. The current technologies, materials, equipment, and structures offer challenges to the basic assembly of these new devices while still not adequately addressing cooling and reliability concerns.
The envelope of technical capability of next level interconnect assemblies are not yet known, and no clear cost effective technology has yet been identified. Beyond the performance requirements of next generation devices, the industry now demands that cost be a primary product differentiator in an attempt to meet profit goals.
As a result, the road maps are driving electronics packaging to precision, ultra miniature form factors which require automation in order to achieve acceptable yield. These challenges demand not only automation of manufacturing, but also the automation of data flow and information to the production manager and customer.
There have been many approaches to addressing the advanced packaging requirements of microprocessors and portable electronics with successive generations of semiconductors. Many industry road maps have identified significant gaps between the current semiconductor capability and the available supporting electronic packaging technologies. The limitations and issues with current technologies include increasing clock rates, EMI radiation, thermal loads, second level assembly reliability stresses and cost.
Current approaches to package advanced processors are based upon using discretely packaged components on an interconnect substrate to complete the processor-cache function. However, the parasitics associated with each of the packages and the board level interconnections reduces the potential clocking speed and the performance of the processor module.
In an attempt to combat this speed limitation, semiconductor manufacturers have integrated the level 2 cache into the processor die itself. This approach also has limitations, since the amount of cache memory which can be integrated may be constrained by the overall size of the die and the associated cost of a much larger semiconductor device. The limited size of semiconductor-based level 2 cache has a profound impact on the performance gain experienced by limiting the benefit of increased system DRAM memory.
Thermal performance of present and future generation processors will greatly impact the lifetime, functionality and performance of the system. As transistor geometries continue to shrink, the associated heat flux density and power generated in the semiconductor continue to grow exponentially with the square of the clock frequency.
There have been a number of claims by Intel and other semiconductor manufacturers that their warranties would be voided should the designed thermal solution be altered in any way. The above challenges underline the need for an efficient thermal path between the die and the ambient environment.
As semiconductors continue to increase in switching rates and products increase in feature and component density, the concern for EMI protection within the product and to the environment may be enhanced. The magnitude of EMI radiation may be related to the interconnect length between active components distributed on the substrate. Many approaches have been developed to shield problem components. These approaches include discrete metal shields and metallized enclosures, but may be costly and involve an iterative design process for evolving form factors and device types. Inherent package shielding may be necessary for next generation processors and microelectronic applications.
A major problem facing the implementation of Ball Grid Array (BGA) packages is the reliability of the solder-based connection. The primary failure mechanism may be cracked balls due to stress incurred by the Coefficient of Thermal Expansion (CTE) mismatches between the package and the board. Studies have shown that the standoff height of a large ball offers a measure of compliance that increases overall reliability.
As pin counts increase and package sizes decrease, the industry will be forced to move to finer pitch arrays and smaller balls which may be less reliable. The use of under-fill has reduced some of these concerns, but the re-workability of an under-filled component may be poor at best. This problem has motivated many companies to investigate a de-mountable assembly technology.
Traditionally, Multi-Chip Modules (MCMs) have been defined as any package with more than a single semiconductor device. Today, there is a new paradigm, only those packages with high die count (e.g., ten or more) using complex processes may be considered MCMs. The industry has adopted the Multi-Chip Package (MCP) as the means to achieve high levels of functional integration. An MCP may be defined generally as a multi-chip package with fewer than ten devices.
These fewer chip packages (MCPs) offer many of the benefits of MCMs, but utilize standard processes and materials to complete the package. One of the downsides to the use of MCMs may be the impact of non-yielding semiconductors on first-pass yield and subsequent rework. One motive for using MCPs may be the exponential cost of further wafer scale integration and Systems On a Chip (SOC).
The use of MCPs allows a semiconductor manufacturer to partition an overall function into smaller more testable and higher yielding devices which may be integrated into a single package. The microprocessor industry is a perfect example, as there have been great efforts to integrate features such as Level 2 cache into the processor die itself. Such integration efforts have not been completely addressed through using MCPs. However, the use of fewer devices increases the first pass yield and reduces overall cost. Regardless, there is a need for improved partial and full speed testability for both MCMs and MCPs.
The development of a novel packaging technology for the commercial microprocessor market may enable GigaHertz processors to be manufactured at a low cost. The ability of the packaging technology to allow high speed communications in a reliable fashion between a separate cache and microprocessor may eliminate the need for on-die cache and provide a path for lower cost microprocessors.
The need for an extremely large and typically low yield microprocessor die may be mitigated with this new packaging technology. Furthermore, the future road map for GigaHertz processors may be directed towards a de-centralized approach whereby the high speed interconnect, a very reliable package for multiple die, and excellent thermal and EMI package characteristics may allow for low cost commercial GigaHertz personal computers.